1. Field of the Invention
The present invention relates to a one- or two-dimensional photoelectric conversion apparatus used for a video camera, a digital camera, a facsimile, an image scanner, a digital copier, an X-ray image pickup apparatus or the like which reads an image. More particularly, the invention relates to a photoelectric conversion apparatus capable of eliminating noises.
2. Related Background Art
In the field of photoelectric conversion apparatus, various types of apparatuses have been proposed including in addition to a CCD, a BASIS having a bipolar transistor at each pixel as an amplification element, a photoelectric conversion apparatus having a MOS transistor at each pixel as an amplification element (e.g., Japanese Patent Laid-Open Application No. 1-154678) and the like. In such amplification type photoelectric conversion apparatuses, performance variation of amplification elements at respective pixels produces fixed pattern noises (FPN). Various methods of eliminating FPNs have been proposed heretofore. Of these, one method proposes to correct a performance variation of amplification elements in accordance with a difference between a light signal (signal S) and a dark state signal (signal N). This method will be described with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram of one bit of a one-dimensional photoelectric conversion apparatus, and FIG. 2 is a timing chart (refer to The Institute of Television Engineers of Japan, Vol. 47, No. 9 (1993), p. 1180).
The circuit operation and FPN elimination will be described hereinunder. First, a control pulse .phi..sub.CR is turned on to reset storage capacitors CT 1 and 2. Next, after charges corresponding to incident light are applied to the base of a bipolar transistor 9 which is a sensor and the charges are stored, a control pulse .phi..sub.TS is turned on to transfer a light signal containing noises to a light signal capacitor CTS 1. Next, a control pulse .phi..sub.BRS is turned on to reset the sensor and then a control pulse .phi..sub.TN is turned on to transfer a sensor noise signal to a noise signal capacitor CTN 2. Thereafter, the control pulse .phi..sub.BRS is again turned on to reset the sensor and resume the storage operation.
During the storage operation, a shift register SR starts scanning. First, a light signal common output line 3 and a noise signal common output line 4 are reset by reset MOSs 5 and 6, and thereafter, data in the light signal capacitor CTS and noise signal capacitor CTN are output to the common output lines 3 and 4 through capacitance division by common output line capacitances 7 and 8. These common capacitances CHS 7 and CHN 8 are capacitances of the common output lines 3 and 4. The capacitance of the light signal common output line 3 is hereinafter defined as the output line capacitance CHS 7, and the capacitance of the noise signal common output line 4 is hereinafter defined as the output line capacitance CHN 8. Thereafter, the output line capacitances CHS 7 and CHN 8 are again reset to read CTS and CTN data of an unrepresented next bit.
The above operations are repeated to output data of all bits. Output signals are input via voltage followers 13 and 14 to a differential amplifier 15 to deliver a final output signal of an IC constituting the photoelectric conversion apparatus. FPNs in the chip are generated because of a variation of h.sub.FE and the like of bipolar transistors at respective pixels. The above-described S-N method can eliminate FPNs to be caused by a variation of h.sub.FE of bipolar transistors.
FPNs are fixed pattern noises in a dark state. FPNs are hereinafter defined as fixed pattern noises in a dark state.
A conventional FPN elimination method will be further detailed. In FIG. 1, a signal (Sout) on the light signal common output line and a signal (Nout) on the noise signal common output line are given by the following equations (1) and (2). EQU Sout=[(V.sub.S .times.C.sub.TS)+(V.sub.CHR .times.C.sub.HS)]/(C.sub.TS +C.sub.HS) (1) EQU Nout=[(V.sub.N .times.C.sub.TN)+(V.sub.CHR .times.C.sub.HN)]/(C.sub.TN +C.sub.HN) (2)
where VS is a voltage across the light signal capacitor CTS when a light signal is read, and VN is a voltage across the noise signal capacitor CTN when the noise signal is read.
If CHS=CHN=CH, VS=VN=VCT (in a dark state), and CTS=CTN=CT in the equations (1) and (2), then a difference (Sout-Nout) is 0.
Even if there is a variation of VCT at respective pixels, FPNs can be eliminated because the difference (Sout-Nout) is 0.
With the above-described S-N method, FPNs can be eliminated if the light signal capacitor CTS and the noise signal capacitor CTN have the same value.
However, in practice, there is an unbalanced quantity between the capacitance values of the light signal capacitor CTS and the noise signal capacitor CTN, the unbalanced quantity being caused by irregular process precision degrees. The inventors of the present invention have found that this unbalanced quantity causes FPNs.
If there is an unbalanced quantity .DELTA.CT between the capacitance values of the light signal capacitor CTS and the noise signal capacitor CTN, i.e., if CTS=CT+.DELTA.CT and CTN=CT, then the difference signal (Sout-Nout) is given by the following equation (3). EQU Sout-Nout={.DELTA.CT/(CT+CH)}.times.{CH/(CT+CH)}.times.(VCT-VCHR)(3)
Specifically, FPNs become proportional to the unbalanced quantity between the capacitance values of the light signal capacitor CTS when the light signal is read and the noise signal capacitor CTN when the noise signal is read.
Therefore, even if there is some unbalanced quantity, FPNs can be made minimum if a difference between a voltage VCT across the capacitor CT and a reset voltage VCHR of the output line capacitance CH is made small.
However, if the voltage VCT across the capacitor CT changes with irregular process precision degrees or operation conditions (e.g., supply voltages and operation frequency), a difference between the voltage VCT across the capacitor CT and the reset voltage VCHR of the output line capacitance CH also changes. Therefore, a variation of FPNs is caused by irregular process precision degrees and operation conditions, which variation is not preferable in practical use.
For example, in the conventional circuit shown in FIG. 1, the voltage VCT across the capacitor CT is mainly determined by h.sub.FE and base/collector capacitance Cbc of a pixel bipolar transistor, the capacitor CT, a read time of the capacitor CT, and the like. The reset voltage of the output line capacitance CH is fixed to a ground level. Therefore, if h.sub.FE and base/collector capacitance Cbc of a bipolar transistor change with irregular process precision degrees or the read time of the capacitor CT changes with a fluctuation of an operation frequency, then the voltage VCT across the capacitor CT changes so that FPNs depend upon irregular process precision degrees and a fluctuation of an operation frequency.
In the case of an amplification type photoelectric conversion apparatus having a photodiode and MOS amplifiers at each pixel, the voltage VCT across the capacitor CT is determined by threshold voltages Vth of MOS amplifiers and a reset voltage level of the photodiode. Therefore, if Vth of MOS amplifiers and the reset voltage level of the photodiode vary with irregular process precision degrees, a variation of FPNs also occurs.
The conventional FPN elimination method is therefore accompanied with a variation of FPNs to be caused by irregular process precision degrees and operation conditions, which variation is a great obstacle against the S/N improvement of a photoelectric conversion element.